1. Field of the Invention
Embodiments of the invention generally relate to the field of graphics processing. More specifically, the present invention relates to utilization of memory bandwidth within graphics processors.
2. Description of the Related Art
It is a well known conundrum that software engineers like to structure data in forms that are less than optimal for the target hardware that it runs on, and hardware engineers like to design hardware that is not optimal for software engineers. In terms of vertex structures it is very common to specify vertex attributes along with the vertex in memory. However, if only the vertex position is used for most computation a large portion of the cache and thus memory bandwidth is not utilized efficiently. The Data Type Aligned Cache utilizes a vector line size and allocates based on the byte address of the data structure. This allows the cache to cache vectors, or other data types, not blocks of memory which results in an extremely dense cache in terms of geometric primitives.
In terms of vertex structures it is very common to specify vertex attributes along with the vertex in memory. These structures will eventually be allocated in a data cache. The vertex positions can be different from frame-to-frame, causing low data cache hit rates on vertex positions data. If only the vertex position is used for most computations, a large portions of the cache, and thus memory bandwidth, are not utilized efficiently. Ideally, data that will be reused, i.e. local variables, will be stored in the graphics processing engines integer unit data cache (core data cache). This will increase the hit rate in the cores data cache.